Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor
Network-on-Chip (NoC) is a promising solution for efficient interconnection between processor cores in Chip-Multi-Processor (CMP). This paper is focusing on the energy-efficient design of buffers, a group of the most important components in NoC. From our investigation, an overwhelming majority of “zero” is contained in the packets transmitting in NoC for CMP. A zero-efficient buffer design is proposed as well as the error control scheme. Compared with conventional design, up to 43% energy consumption can be saved. We use a 90nm CMOS process in our simulation.
An Innovative Power-Efficient Architecture for Input Buffer of Network on Chip
In recent years, the power efficiency of NoC (network on chip) is becoming a new research direction. For tiled CMP (single-chip multi processor), the characteristics of transmission data of NoC in a tiled CMP should be noticed that the probability of which the transmitted bits are zero is much bigger than that of which the bits are one. This paper proposes an innovative powerefficient architecture of input buffer of NoC, which makes use of the mentioned characteristics, can improve the power efficiency of the NoC of tiled CMP significantly.
Adaptive Clock Gating Technique for Low Power IP Core in SoC Design
Clock gating is a well-known technique to reduce chip dynamic power. This paper analyzes the disadvantages of some recent clock gating techniques and points out that they are difficult in System-on-Chip (SoC) design. Based on the analysis of the Intellectual Property (IP) core model, an adaptive clock gating (ACG) technique which can be easily realized is introduced for the low power IP core design. ACG can automatically enable or disable the IP clock to reduce not only dynamic power but also leakage power with power gating technique. The experimental results on some IP cores in a real SoC show an average of 62.2% dynamic power reduction and 70.9% leakage power reduction without virtually performance impact.
- Author: Xiaotao Chang, Mingming Zhang, Ge Zhang, Zhimin Zhang, Jun Wang
- Published on ISCAS’07
An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects
As the gap between processing capability and bandwidth requirement of microprocessor increases, optical interconnects are used more and more widely in chip-to-chip data links. Trade-offs are made among latency, area, power consumption and reliability in the high frequency interconnect system in which error control schemes are always implemented to make it tolerate PER (packet error rate). In this paper, a scalable system for chipto-chip optical interconnects is proposed and different types of error control schemes are compared using 90nm CMOS process. The goals are set to low latency, small area and low power consumption as well as acceptable MTTF (mean time to failure) for USR (ultra-short-reach) with very low BER (bit error rate). After that the ECS-HC based system is picked out and validated based on FPGA and 4.25Gbps 850nm optical transceivers.
- Author: Jun Wang, Kun Huang, Ge Zhang, Weiwu Hu, Feng Zhang
- Published on ISCAS’07
An Effective Approach For Subtreshold And Gate Leakage Power Estimation Of SRAM
The leakage current in SRAM is the vital factor for the low power processor design. In this paper we develop a fast approach to calculate the total leakage power of SRAM, considering the subthreshold leakage (I_sub) and gate leakage (I_gate). This method is proposed on the SRAM special architecture, using the stack factors as the average factor to compute the Isub and using the statistical algorithm to estimate the gate leakage power. The method does not need to be much considered on the working state of SRAM and it can be applied without much spice simulation and suitable for SRAM leakage power computing at the different process. We use this method to test a number of SRAM circuits in the 0.18um, 0.13um, 90nm and 65nm technology and demonstrate the accuracy within less than 5% of hspice on average. This technique is much useful for the system designers to estimate the power earlier, and can effectively improve the power management of the processors and shorten the design time.
- Author: Feng Zhang, Ge Zhang, Yi Yang, Jun Wang
- Published on ICIT’07
Energy-Efficient Input Buffer Design using Data-Transition Oriented Model
Network-on-Chip (NoC) has been proved to be an efficient solution for interconnection between processor cores in Chip Multi-Processor (CMP), which will consume extra energy. This paper is focusing on the energy-efficient design of input buffer, one of the most critical components in NoC. For precise calculation of energy, data-transition oriented model with multilevel simulations is proposed here. And using our method, a suit of benchmarks, SPLASH-2, are executed to evaluate the designs with different physical parameters and circuit structures. The simulations are based on 90nm CMOS process, and the input buffer with 64-bit width and 16-entry depth is recommanded for more energy-efficiency.
- Author: Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Tang
- Published on ISIC’07
A Physical-Annotation-Based Power Modeling and Estimation Method for Processor
The proposed method is focused on synthesis-based static circuits, and a power modeling library is developed for modeling processors by means of parametric RTL and physical annotation,and all kinds of processor modules are mapped into combinations of basic components. Those models are linked to an architectural simulator, running benchmarks to get power results. The power analysis of benchmark platforms proves to be effective and highly correlated, with an average 10% error and little speed penalty compared with the gate-level power analysis.
- Author: Kun Huang, Ge Zhang, Jun Wang, Hongbo Zeng
- Published on JCAD’07
A Hierarchy UPF Driven Low Power Flow in a 28nm Semi-Custom Design
To achieve ultra-high performance, we used a semi-custom design approach, which brought in some differences compared with standard low power flow by Synopsys. In our 28nm design, hierarchy UPF were used to describe power intent contains power shut-off domains, always-on domains, analog front-end hard macros, retention memories and isolation cells. In DC, UPF was loaded to insert isolation cells for a large number of memories in semi-custom designed gatelevel netlist and a few synthesized blocks; in MVRC, UPF was used to check power intent against gate-level and post-PnR PG netlist. For different usages, slightly different UPFs were used. This paper describes our low power implementation and verification flow driven by hierarchy UPF in Marvell, as well as some useful experience and tips from our work.
- Author: Jun Wang
- Published on SNUG’12