Reading Note of “Closing gap between ASIC and Custom Design”

Chapter 1: Custom vs. ASIC

1. Microarchitecture

pros: better pipeline

cons: less choices (ASIC can compare different microarchitecture choices with much less effort)

2. Timing overhead

pros: latch-based pipeline

3. logic style

pros: dynamic logic

4. logic design

pros: more layout aware (ASIC is catching up fast with adoption of DCT, and can try out different choices easily)

5. cell design

pros: more sizing and shorter wires 6. process variation cons: ASIC can port between different processes much easier

Chapter 3: Principles of Latch-Based Pipeline

Latch basics

  • Active high = transparent high
  • 2 different clock to Q delay numbers: ck2q (while opaque) & d2q (while transparent)

Chapter 15: Use ASIC Methodology to Achieve Custom-Like Timing in Read Channel SP4140 of TI

  • Different circuits have different proper clocking style. Latch-based pipeline doesn’t suit for everybody. FIR use latch and Viterbi use flip-flop, because the latter has combinational feedback.
  • To achieve higher frequency, duplication and parallization are used in FIR. This is a trade-off between area and frequency.
  • ASIC methodology can achieve better timing with custom flip-flop and careful “prescribed” clock tree.
    • Sense-amplifier-based flip-flop (SAFF) is used here.
  • Reduce uncertainty can improve performance. Refer to Chapter 13/14.

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