Moore’s Law challenges below 10nm (my log on ISSCC 2015 evening session)

Bohr: moore’s law for 50 years

  • $/mm2 is increasing since 130nm
  • heterogeneous intergration: 3D chip is not a replacement of moore’s law (quite opposite with Sehat)
  • refocus on general purpose design

Hill: 21 century computer architecture

  • 21stcentruryarchitecturewhitepaper.pdf
  • instruction set is not going to be untouchable anymore
  • energy first
    • parallelism
    • specialization
    • cross-layout design
  • cross-cutting: break current layers with new interfaces
    • BREAK LAYERS
  • software bloat
    • PHP is 50x slower than BLAC
  • 3D stack
    • how to address thermal problem? the power is reduced by 3D stacking

Madden

  • cost per added layer is also increasing
  • IO bandwidth requirements grow by >2.2x / generation
  • 3D stacking!!!
    • stack different tech allows I/O to disappear
    • breaking the Tyranny of defect density: small area , low cost

Sun (TSMC)

  • Future of semiconductor: MEB, EUV
    • EUV got delayed because of cost
  • challenges: non-scalale or incompatible specialty features
  • 3Dx3D
    • energy efficient chip scaling
    • new computer architecture
  • EUV has a bit break these days, good news to scalling down further more

Yeap

  • mobile soc
    • cost is the most important
  • 28nm is the sweet spot
  • time to yield >> effective die cost: defects, variation, leakage
  • too busy 1-D scaling: 4~2 years to 1.5yr/node
    • no time to be creative
  • need to harvest the values of sweet nodes
    • enhanced 28nm for utlra low power wearable and IoT

De Boeck

  • maximizing functionality and reducing power cost effectively, with application focus
    • application drive tech scaling
  • beyond CMOS devices
  • inter-core wiring

Q&A

Question: Why always cost, how about performance of transistors while scaling down?

Answer: market has changes. interconnect bottleneck is hard to achieve with higher freq. And power as well. Consumer end, power > performance.

Question: Breaking layers?

Answer: look at Apple. maybe the hardware company need to change. software company change from selling software to selling service, and to selling ads.

Question: 3D

Answer: the vertical interconnect is too slow – Bohr. real vertical devices, not FinFET? what is that?

Question: hardware designer job security

Answer: circuit design is becoming complecated: more masks, more IP in one SoC. assembling other than building from scratch

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