(TODO)On-chip network for multi-core CPU

This all started from a visiting professor who gave a speech on their recent research on NoC (network-on-chip). From that speech, many of my peers and I have reached a common agreement that although it’s not very hot currently NoC research would become more and more concentrated on. As the SoC (system-on-chip) was going to integrate more and more IPs, the communication between these IPs would be a serious bottleneck if we continued to use bus or crossbar for interconnection. By bringing network ideas onto a single chip, individual IPs are recognized as network nodes and packages are used to containing data. Comparing with crossbar structure, lots of interconnection resources will be saved, as well as power consumption. Comparing with bus structure, NoC is more adaptive and more efficient.

Low power NoC structure

Although NoC has brought concepts and experiences from well-established computer networking, there are still lots of significant differences. For example, NoC always have to balance efficiency, power and area, and limited routing resource can limit the network structure.

To carry on-chip data, packages in NoC was designed very small, usually 64-bit to 256-bit. This would reduce the requirement of buffering, which can consume most of the power and area, and also the latency from source to destination. Part of my work was to find an appropriate size of package, giving the application as CPU core to CPU core, and balance the efficiency, power and area.

arbitration strategy

network structure

Power models

buffer

crossbar

interconnect

Simulation environment

CMP simulator

NoC simulator

My innovation

Unbalanced 1’s and 0’s in data

low power buffer

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