Reading Note of “SystemVerilog for Design” (Chapter 6: SystemVerilog Procedural Blocks, Tasks and Functions)

“always” procedual block

  • Verilog limitation
    • “always” could be combinational or latched or sequential
    • EDA tool must infer design intent from cotent, which might differ from the real intent
  • SystemVerilog improvement
    • New keywords: “always_comb” & “always_latch” & “always_ff”
  • “always_comb” (adv. vs. “always @ *”)
    • NO need to specify sensitivity list, auto infer
      • Eliminate the risk of incorrect sensitivity list
      • Includes the signals read within any functions called from the block
        • Some functions may not list all the signals their read as argument
    • Assignment only happens in current block, to avoid multi-driven problem (which is legal in Verilog syntax)
    • Clear design intent
      • Tool will issue warning if content doesn’t represent combinational logic
    • Automatic evaluation at time zero, after initial/always activation
      • Important for some special case to get correct init value, instead of default value. The book here gave a very interesting corner case of a state machine, at page 145.
  • Extra good practice tip about break-down code into managable pieces: multi always block vs. functions
    • Multi-always: many signals propagate through several procedural blocks
    • Function is better (maybe even better if use unit test)
  • “always_latch”
    • Same sensitivity list inferring with “always_comb”
  • “always_ff”
    • Tool will verify if content represent sequential logic (synthesize requirement)
      • Every signal in the sensitivity list must be qualified with “posedge” or “negedge”
      • Event control must be from sensitivity list


  • Inferred “begin … end”
  • “return”
    • Return variable explicitly, instead of using function name variable
    • End function before going through to the end of code
  • “void” type function (C-style)
    • No return function
    • But can have “output”
  • For synthesis, use “function void” instead of “task”
  • Argument
    • Named argument when using
      • Ex. divide(.denominator(b), numerator(a));
    • “input/output/inout” argument
      • By default, “input”
    • No argument
      • To break-down code into managable pieces
    • Default value
      • Missing argument when using
    • Arrays, structures and unions as argument
      • Use “typedef”
    • Reference instead of copy
      • Normally, inputs are copied when called, outputs are also copied when finished
      • Verilog still can use “reference” with hardcoded hierarchical name of signals. But it’s very poor in reusablility.
      • New “ref” keyword (instead of input/output/inout)
        • Only automatic task/function can have “ref” arguments
      • New “const ref” keyword to define read-only reference arguments
      • (used in task) Allows sensitivity to changes
        • Can be used to trigger event
        • Can be used to read/write value in real-time (if have event/timing control)
    • Restriction with “output/inout/ref” argument
      • Not from an event expression
      • Not from a continuous assignment
      • Not from outside procedural statement
  • Named task/function: better readability
    • endtask : <task_name>
    • endfunction : <function_name>
  • Empty task/function as place holder

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