Reading Note of “SystemVerilog for Design” (Chapter 2: SystemVerilog Declaration Spaces)

Package

  • Verilog shortage: no global declaration
  • package … endpackage
    • share user-defined type definitions across multiple modules
    • independent of modules
    • parameters cannot be redefined
      • parameter == localparam in package, while in module localparam cannot be directly redefined while instantiation
  • referencing
    • “::” the scope resolution operator
      • package_name::package_member
    • import
      • import package_name::package_member
        • importing an enumerated type definition donot import the labels
      • import package_name::*
        • what is used will be imported
    • $unit declaration space
  • synthesis guide
    • tasks and functions must be “automatic”
      • storage for automatic task/function is allocated each time it’s called
    • cannot use “static” variables

$unit: compilation-unit declarations

  • declaration space outside of package/module/interface/program
    • BUT it’s not global
  • variables and nets in $unit
    • source code order can affect the usage of a declaration external to the module
  • each compilation has one $unit
    • single-file compilation
    • multiple-file compilation: source order
  • coding  guide
    • DONOT make any declarations in $unit space
    • import packages into $unit
      • ILLEGAL to import the same package more than once into the same $unit
 // filename: def.pkg `ifdef DEF_PKG `define DEF_PKG package def; // ... endpackage `endif // in every design or testbench file that need package "def" `include "def.pkg" // NOTE: donot work for global variables, static task/function 

  • identifier search rules
    • 1) local
    • 2) package
      • 2.1) named first
      • 2.2) * wildcard second
    • 3) $unit
    • 4) design hierarchy
  • synthesis guide
    • use packages instead of $unit
    • external task/function must be automatic

Unnamed statement blocks

  • local variables in named blocks can be accessed hierarchically
  • local variables in unnamed blocks (added in SV) has no hierarchical path
    • protecting from external, cross-module referencing

Timing units and precision

  • problem with Verilog’s timescale directive: file order dependent
  • SystemVerilog improvements
    • time value with time units: 5ns, 3.2ps
      • no space
    • scope-level time units and precision: timeunit & timeprecision keywords
      • must be immediately after module/interface/program declaration
    • search order
      • 1) local
      • 2) parent module/interface
      • 3) `timescale in effect while compilation
      • 4) defined in $unit
      • 5) simulator default
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