Reading Note of “SystemVerilog for Design” (Chapter 3: SystemVerilog Literal Values and Built-in Data Types)

Literal value enhancement

  • Fill vector with all ones
    • Verilog tricks
      • data = ~0; // one’s complement
      • data = -1;  // two’s complement
    • SystemVerilog: apostrophe(tick) ( ‘ ) (Note: not back-tick ( ` ))
      • data = ‘1; // all 1’s
      • data = ‘z; // all z’s

DEFINE enhancement

  • String
  1. // Verilog 
  2. `define print(v) $disp    lay(“variable v = %h”, v) 
  3. `print(data); // = $display(“variable v = %h”, data);
  4. // SystemVerilog 
  5. `define print(v) $display(`“varaible v = %h`, v) 
  6. `print(data);  // = $display(“variable data = %h”, data); 
  7. // SystemVerilog: escape with double ` 
  8. `define print(v) $display(`“varaible `\`”v`\`” = %h`”, v) 
  9. `print(data);  // = $display(“varaible \”data\” = %h”, data); 
  • Construct identifier names: double “ w/o space will separate names that will allow 2 or more names to be replaced and form a new name.
  1. `define MY_NET(index) bit my_net“index“_bit; 
  2. `MY_NET(00)  // = bit my_net00_bit; 
  3. `MY_NET(15)  // = bit my_net15_bit; 

    Variables

  • Type
    • Net: “wire” keyword, only 4-state
    • Variable: “var” keyword, most of the time it can be omitted
  • Data type: value system
    • 2-state: “bit” keyword
    • 4-state: “logic” keyword (to replace “reg” keyword)
  • Explicit & implicit (shit-hole of SystemVerilog)
    • 4-state 8-bit varaible: logic [7:0] busA; // to be explicitly: var logic [7:0] busA;
    • 2-state 32-bit variable: bit [31:0] busB; // to be explicitly: var bit[31:0] busB;
    • 4-state 8-bit net: wire [7:0] busC; // to be explicitly: wire logic [7:0] busC;
    • wire reg [31:0] busD; // ILLEGAL
  • Signed vs. Unsigned
    • Concatenation automatic create “unsigned” result
    • “logic” are unsigned by default
    • “int” are signed by default
    • <type> <signed/unsigned> <bit width> <name>;
  • Synthesis guideline
    • Because 2-state data types begins simulation with default 0 instead of X, if they are used in RTL may cause RTL behavior mismatch gate-level netlist.
    • Converting from 4-state to 2-state, X and Z are mapped to 0
  • High level data type:
    • 2-state data type; used for abstract model or DPI (Direct Programming Interface) to work with C/C++ model
      • “byte”: 8-bit
      • “shortint”: 16-bit
      • “int”: 32-bit
      • “longint”: 64-bit
    • “void”: no storage
    • “shortreal”: 32-bit single-precision = float in C, while “real” = double in C
    • “classes”: not covered in this book
  • Most signals can be declared as “logic” in RTL
    • “logic” for single-driver
    • “wire” for multi-driver logic (wand/wor)
  • Value drivers
    • Any number of “initial” or “always” blocks (back-compatable with Verilog which is not really circuit behavior)
    • Single “always_comb/always_ff/always_latch” block
    • Single “assign” statement
    • Single module/primitive output/inout
  • Type casting
    • Static casting (synthesizable)
      • Size casting: <size>'(<expression>)
        • 16′(2) // 16-bit wide
      • Sign casting: <sign>'(<expression>)
        • signed'({a, b}) // unsigned concatenation result to signed
    • Dynamic casting (has error check)
      • $case(dest_var, source_exp);
  • Varaible initialization
    • SystemVerilog in-line initialization is before time zero and does not cause a simulation event
    • Testbench should initialize varaibles to their inactive state
  • Static and automatic variables
    • “static” vs “automatic”
      • Storage
      • Automatic variables can be used for re-entrant tasks and recursive functions.
    • Module level, all varaibles are static
    • “begin … end” and “fork … join” blocks, tasks and functions, all storage defaults to static
    • Automatic tasks and functions have all automatic storages
    • Initialization
      • Static variables are only initialized once
      • Automatic variables are initialized each call

Constants

  • Verilog
    • “parameter”: can be redefined when instantiation
    • “specparam”: can be redefined from SDF
    • “localparam”: elaboration-time constant, cannot be directly redefined
  • SystemVerilog: C-like const keyword
    • const int N = 5;
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