Reading Note of “SystemVerilog for Design” (Chapter 4: SystemVerilog User-Defined and Enumerated Types)

“typedef” keyword

Ex. typedef int unsigned uint;

  • Local & shared
    • Local: within a module/interface, scope is limited locally
    • Shared: use package and import; or import to $unit
  • Naming convention
    • End with “_t” as C

Enumerated types

  • Verilog vs SystemVerilog
    • Verilog: use constants to represent enumerated types
      • But nothing would limit the value of enum varaibles, will cause error
      • Need “full case” directive
    • SystemVerilog: enum
      • Self-doc, easier to debug
      • Value check
      • All tools deal with enum the same way
  • “import package_name::*”
    • Import the enum type will not automatically import labels
  • Define list of labels
  1. enum {RESET, WAIT[2], WORK[3: 5], CLEAN[3: 0]} state;
  2. // RESET, WAIT0, WAIT1, WAIT2, WORK3, WORK4, WORK5, CLEAN3, CLEAN2, CLEAN1, CLEAN0 (“[” and “]” are discarded) 
  • Lable
    • Must be unique in naming scope
  • Values
    • Default to be “int” and start from 0
    • Can be specified explicitly
      • One-hot, one-code, Johnson-count, Gray-code, etc.
    • Must be unique
  • Types
    • Default to be “int”
    • Can be specified explicitly
      • Bit, logic
      • Ex. enum logic [2:0] {WAIT = 3’b001, LOAD = 3’b010, READY = 3’b100} state;
    • 4-state could be Z or X
      • But the next lable after Z or X should be given value explicitly (otherwise tools don’t know how to increase value automatically)
  • Typed enumerated type vs. anonymous enumerated type
    • “typedef enum {WAIT, LOAD, READY} state_t;”
  • Type check
    • Most variables are loosely typed
      • Any value can be assigned to a variable, just has to be cast implicitly
    • Enum is strongly typed
  1. typedef enum
  2.     WAIT, LOAD, READY 
  3. } state_t; 
  4. state_t state, next_state; // actually is stored as int 
  5. int foo;
  6. state = next_state; 
  7. foo = state + 1; 
  8. state = foo + 1; // ILLEGAL 
  9. state = state + 1; // ILLEGAL 
  10. state++; // ILLEGAL 
  11. next_state += state; // ILLEGAL 
  • Casting
    • next_state = state_t'(state++); // legal: synthesizable, no value check, maybe out-of-range
    • $case(next_state, state + 1); // legal: not synthesizable, with value check, slower in simulation
  • System methods (similar to C++ syntax)
    • <enum_varaible_name>.first/last/next(<N>)/prev(<N>)/num/name
      • *.name return a string
      • If current value is not a valid value defined, next/prev return the first element
      • *.next/prev will wrap around
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