Reading Note of “SystemVerilog for Design” (Chapter 5: SystemVerilog Arrays, Structures and Unions)


  • Struct vs. array
    • Array: collection of elements with the same type and size; reference by index
    • Struct: collection of varaibles/constants can be diff types and sizes; reference by name
  • Struct vs. interface
    • Struct usually for variables, can be defined inside of interface
    • Inferface are net type, cannot be defined inside of struct
  • Use “typedef” to give a name to “struct” and reuse it
  • Assigning value to structures
    • New “‘{ }” token
      • IW = ‘{100, 5, 8’hFF, 0};
    • By name
      • IW.a = 100; IW.b = 5;
    • Combine these two
      • IW = ‘{address:0, opcode:8’hFF, a:100, b:5}
    • Default value
      • IW = ‘{default:0}; // all members by default is 0
      • IW = ‘{default:0, a:100}; // all members is 0 by default, except a is 100
  • Packed vs. unpacked
    • By default, it’s upacked
    • Use “packed” keyword to defined packed structure
      • All members are stored as contiguous bits
      • Then members can be reference as vector with bit/range position.
      • Can only contain integral values (not real or shortreal)
      • “signed” or “unsigned”
        • Treat the whole vector of packed structure as singed/unsinged
        • Each member can still be signed/unsigned independently
  • Passing struct through module/interface ports and task/function argument
    • NOTE: when passing unpacked struct, both sides should have exactly the same type, while anonymous struct declared in 2 diff modules, even if with the same names/members, are not the same type of struct
  • Synthesis guide
    • Both unpacked and packed struct are synthesizable


  • Union is a single storage element that can have multiple representation
    • Ex. One 8-bit data can either be signed or unsigned with diff configuration
  • The same with struct, use “typedef” to reuse
  • Unpacked union
    • NOT synthesizable
  • Tagged union
    • “tagged” keyword
    • Check whether the union is used in a consistent way
      • Write to one member, then read from another is dangerous
  • Packed union
    • Synthesizable
    • All memebers have the same size
      • Allow write to one format then read from another
  1. // example: represent packed struct in array of bytes 
  2. Union packed { 
  3.     data_package_t packet; // packed structure 
  4.     logic[7: 0][7: 0] byte; // packed array 
  5. datareg; 


  • Unpacked arrays
    • Verilog limitation: restrict access to arrays to just one element of the array at at time
      • SystemVerilog refer Verilog style array as unpacked arrays
      • Elements are stored independently, just grouped under the same array name
    • SystemVerilog improvement: reference the entire/slice of an array
      • A slice is one or more contiguously numbered elements within one dimension of an array
      • Assignment of this type: left-hand & right-hand should have identical layout and types
    • Simplified declarations
      • logic [31:0] data [1024]; // logic [31:0] data [0:1023]
  • Packed arrays
    • Vector = packed arrays
      • Any vector operation can be performed on packed arrays
    • Only bit-wise types can be packed arrays
      • Bit/logic/reg or net types
  • Unpacked vs packed arrays
    • Unpacked: model memories & abstract types
    • Packed: vectors with sub-fields
  • Assignment
    • Packed array is assigned the same as vector
      • Concatenated operator, repicate operation
    • Unpacked array
      • ‘{ }” and “‘{n{ }}” keyword
    • Default value
      • Int a [0:7][0:1023] = ‘{default: 8’h55};
    • Copy
      • Unpacked array copy only can between the same array with the same number of dimensions and element size, and are of the same types
  • Indexing

    logic [3:0][7:0] mixed_array [0:7][0:7][0:7];

    ______|-4-||-5-|_____________|-1-||-2-||-3-| <- order

  • Typedef with array
  • Array of struct and union
  • Array in struct and union
  • Passing
    • Any number of dimensions can be passed through ports or task/function arguments
  • “foreach” keyword to iterate array elements
  1. int sum[1: 8][1: 3];
  2. foreach(sum[i, j])
  3. sum[i][j] = i + j;
  • Array query system function
    • $dimensions(array_name)
      • Number of dimension
    • $left/right/low/high(array_name, dimension)
      • Boundary of dimension
    • $size(array_name, dimension)
      • Size of dimension
    • $increment(array_name, dimension)
      • 1 or -1
    • $bits(expression)
      • Size-of “expression”, expression could be any type of data or slices
    • All these system functions are synthesizable
  • Dynamic types are covered in verification that’s NOT synthesizable
    • Dynamic arrays
    • Associative arrays
    • Sparse arrays
    • Strings (character arrays)

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