Reading Note of “SystemVerilog for Design” (Chapter 7 SystemVerilog Procedural Statements)

New opeators

  • “++” & “–” operators
    • “i++” is post-increment, while “++i” is pre-increment
      • i = 10; j = i++; // j = 10, i = 11
      • i = 10; j = ++i; // j = 11, i = 11
    • Behave as blocking assignments, so avoid using them where non-blocking is required
  • Combination of operation with assignment
    • “+=”, “-=”, “*=”, “/=”, “%=”, “&=”, “|=”, “^=”, “<<=”, “>>=”, “<<<=”, “>>>=”
      • Where “<<<” and “>>>” are arithmetic shifting while treating target as signed number, and do sign expansion when needed
  • Wildcard equality operator “==?” and “!=?”
    • Allow don’t care bits: X, Z or ?
    • While original “==” and “!=” will return unknown (bit x) if either operand is X or Z
    • Notice: expand vector to same size before comparison. This can be dangerous.
    • Synthesizable: right hand operand must be constant expressions
  • Membership operator: “inside”
    • if ( a inside {3’b001, 3’b010, 3’b100} ) ó if ( (a==3’b001) || (a==3’b010) || (a==3’b100) )
    • Right-hand value could be array
    • Use X or Z to represent don’t care
    • Can be used in case statement
case (instruction) inside

4’b0???: …

4’b1000, 4’b1100: …

default: …

endcase

 

  • Synthesizable: right hand operand must be constant expressions

Operand enhancement

  • Type casting
    • In Verilog, there is no explicit type casting method
    • type'(expression)
  • Size casting
    • “size'(expression)”
  • Sign casting
    • “signed'(expression)”
    • “unsinged'(expression)”

Enhanced “for” loops

  • Local variables within “for” loop
    • Ex. “ for (int i=0; I <=15; i++)
    • Prevent interference between for loops
    • They are automatic type
    • Doesn’t exist outside “for” loop
      • If want to be used after for loop, must be declared outside
  • Multi “for” loop
    • Ex. “ for (int i=1, byte j=0; i*j < 128; i++, j+=3)
  • Named procedual blocks, to access local variables
    • But variable within “for” loop cannot be accessed hierarchically, must be declared outside “for” loop inside named procedual block

“do … while” loops

  • A while loop might not execute at all
  • Synthesizable: statically determine how many times a loop will execute

“foreach” loops

  • To interate elements of single- and multi-dimentional arrays

“break”, “continue”, “return”

  • C-style jump statements, to replace old “disable” statement
  • More intuitive and concise

Enhanced block names

  • Named “end” to paire with named “begin”
  • For readability

Statement lables

  • For readability
  • <lable> : <statement>
  • Illegal to have both label and name

Enhanced “case”

  • “unique case”
    • = parallel case + full case
    • Runtime check
      • Pros: actual value will be checked, no false alarm
      • Cons: dependent on the thoroughneess of the verification tests
    • Clear design intent
  • “priority case”
    • = full case
    • Runtime check
    • Notice: if it’s not full case, latches can be inferred

Enhanced “if … else”

  • “unique if .. else”
    • The order of the decisions is not important
    • Cannot have overlapping conditions (similar to parallel case)
  • “priority if … else”
    • Clearly defined design intent
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