Module prototypes: extern

  • Similar to C-Style *.h head file
    • More convenient: no duplicate port definition needed
    • Can be defined in one file, then “`include” to other files
  • No necessarily

Named ending statements

  • “endmodule : <module_name>”
  • Also apply for others
    • “package … endpackage”
    • “interface … endinterface”
    • “task … endtask”
    • “function … endfunction”
    • “begin … end”

Nested module

  • Verilog limitations
    • Module names are global
      • No restriction to be accessed
      • Cause name conflicts
  • SystemVerilog improvements: nested module
    • Modules that are declared within modules
    • Not visible outside the scope
      • Can be instantianted by the parent module and the modules below
    • Can also access variable/constant/task/function in $unit
  • However, controversy with common moduel style that every module has it’s own file
    • This kind of style is good for large designs; and good for utilizing VCS
    • Use “`include” to keep the same style

Simplify module instance

  • Named port connection is good for documenting the design intent, but too verbose
  • “.name” connection
    • “.port_name(net_name)” -> “.port_name” if port_name equals to net_name
  • “.*” connection
    • Matches all cases that port_name equals to net_name
  • These simplification also apply to function/task

Net aliasing

  • “alias” statement
    • alias clk = clock = ck; // can be multiple aliases together
    • Only applies for net types, with the same type, and the same size
      • wire [31:0] n1; wire [3:0][7:0] n2; alias n2 = n1;
    • By default, infer “wire” if left-hand side names are not defined explicitly
    • Alias vs. assign
      • Assign is copied from right to left whenever right is changing
      • Alias is copied to all whenever either one is changing
  • Alias with “.name” and “.*” is powerful
    • On top-level module, even if the local net_name is different from the port_name of its instances, we can still use “alias” to make them the same and use “.*”

Passing values through module ports

  • SystemVerilog removes most port restrictions, except the following two
    • Varaible can have only one single source
    • Unpacked types must be identical
      • Declared using the same “typedef” definition

Reference ports “ref”

  • Reference the hierarchical source directly
    • Warning: one variable can be written from multiple source
  • NOT synthesizable

Enhanced port declaration

  • Verilog-2001
    • Port list = <direction> <type> <size> <name>
    • By default, type is wire
  • SystemVerilog
    • The first port’s direction could be optional, by default is “inout”
    • Later on, direction could be optional, by default is the same with previous one

Parameterized types

  • Net, variable of a module could be parameterized

module adder #(parameter
type DATA_TYPE = shortint) (

input DATA_TYPE a, b, // redefinable

output DATA_TYPE sum, // redefinable


logic carry // direction is “output”, the same with sum

);

// …

endmodule : adder

 

module top ();

 

adder #(.DATA_TYPE(int)) int_adder( /* … */ );

adder #(.DATA_TYPE(int
unsigned)) uint_adder( /* … */ );

 

endmodule : top

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