Reading Note of “SystemVerilog for Design” (Chapter 11: A Complete Design Modeled with SystemVerilog)

Interesting part: how to implement a latch-based LUT with SystemVerilog interface

//

// implement LUT (basically an SRAM/Register File with interface in SV)

interface if_look_up_table;

 

parameter
int ADDR_SIZE = 8;

parameter
int ADDR_RANGE = 1 << ADDR_SIZE;

parameter
type DATA_TYPE = logic; // the bit-cell’s type could be reconfigurable

 

DATA_TYPE mem [0:ADDR_RANGE-1];

 

// function to perform write operation

function
void write (

    input [ADDR_SIZE-1:0]     addr,

    input DATA_TYPE         data

    );

    mem[addr] = data;

endfunction : write

 

// function to perform read operation

function
void read (

    input [ADDR_SIZE-1:0]     addr

    );

    return (mem[addr]);

endfunction

 

endinterface

 

 

// Then in circuit where instantiate this LUT

 

typedef
struct
packed {

    logic [`NUM_TX_PORT-1:0] FWD;

    logic [11:0] VPI;

} cell_cfg_t;

 

if_look_up_table #(.ADDR_SIZE(8), .DATA_TYPE(cell_cfg_t)) lut();

 

always_latch
begin

    if (lut_wen) begin

        lut.write(lut_waddr, lut_wdata);

    end

end

 

always_comb
begin

    if (lut_ren) begin

        lut_rdata = lut.read(lut_raddr);

    end

    else
begin

        lut_rdata = ‘hz;

    end

end

 

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