Category: IC Design

Reading Note of “SystemVerilog for Design” (Chapter 10: SystemVerilog Interfaces)

Concepts How Verilog models connects between blocks Directly on physical connections in actual hardware level Disadvantage Port connection must be duplicated in several modules Communication protocols must be duplicated also Duplication leads to mistakes that is hard to debug Changes in spec involves lots of modification Details of connection must be defined in early design … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 10: SystemVerilog Interfaces)

Module prototypes: extern Similar to C-Style *.h head file More convenient: no duplicate port definition needed Can be defined in one file, then "`include" to other files No necessarily Named ending statements "endmodule : <module_name>" Also apply for others "package … endpackage" "interface … endinterface" "task … endtask" "function … endfunction" "begin … end" Nested … Continue reading

Reading Note of “SystemVerilog for Design” (Chapter 8: Modeling Finite State Machines with SystemVerilog)

This chapter gives some simple example of FSM code featuring SystemVerilog new keywords, such as "enum", "always_comb", "always_ff", "unique case". Modeling FSM with "enum" 3 blocks to model an FSM Incrementing state Determine the next state Set output Using "enum" without explicitly specified value Cause mismatch in value between RTL and gate-level netlist Cause difficulty … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 8: Modeling Finite State Machines with SystemVerilog)

Register-based SRAM Read Circuit RTL Example using “generate”

Some parameterized example RTL code for register-based SRAM read circuit using "generate" feature Parameter d = 32; // FIFO depth Parameter w = 64; // FIFO data bit-width logic [w-1:0] mem [d-1:0]; // FIFO memory array logic [d-1:0] rwl; // 1-hot read word line   // read circuit using "generate" wire [w-1:0] word_or; genvar width, … Continue reading Register-based SRAM Read Circuit RTL Example using “generate”

Reading Note of “SystemVerilog for Design” (Chapter 7 SystemVerilog Procedural Statements)

New opeators "++" & "--" operators "i++" is post-increment, while "++i" is pre-increment i = 10; j = i++; // j = 10, i = 11 i = 10; j = ++i; // j = 11, i = 11 Behave as blocking assignments, so avoid using them where non-blocking is required Combination of operation with … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 7 SystemVerilog Procedural Statements)

Reading Note of “SystemVerilog for Design” (Chapter 5: SystemVerilog Arrays, Structures and Unions)

Struct Struct vs. array Array: collection of elements with the same type and size; reference by index Struct: collection of varaibles/constants can be diff types and sizes; reference by name Struct vs. interface Struct usually for variables, can be defined inside of interface Inferface are net type, cannot be defined inside of struct Use "typedef" … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 5: SystemVerilog Arrays, Structures and Unions)

Reading Note of “SystemVerilog for Design” (Chapter 4: SystemVerilog User-Defined and Enumerated Types)

"typedef" keyword Ex. typedef int unsigned uint; Local & shared Local: within a module/interface, scope is limited locally Shared: use package and import; or import to $unit Naming convention End with "_t" as C Enumerated types Verilog vs SystemVerilog Verilog: use constants to represent enumerated types But nothing would limit the value of enum varaibles, … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 4: SystemVerilog User-Defined and Enumerated Types)