Register-based SRAM Read Circuit RTL Example using “generate”

Some parameterized example RTL code for register-based SRAM read circuit using "generate" feature Parameter d = 32; // FIFO depth Parameter w = 64; // FIFO data bit-width logic [w-1:0] mem [d-1:0]; // FIFO memory array logic [d-1:0] rwl; // 1-hot read word line   // read circuit using "generate" wire [w-1:0] word_or; genvar width, … Continue reading Register-based SRAM Read Circuit RTL Example using “generate”

Reading Note of “SystemVerilog for Design” (Chapter 7 SystemVerilog Procedural Statements)

New opeators "++" & "--" operators "i++" is post-increment, while "++i" is pre-increment i = 10; j = i++; // j = 10, i = 11 i = 10; j = ++i; // j = 11, i = 11 Behave as blocking assignments, so avoid using them where non-blocking is required Combination of operation with … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 7 SystemVerilog Procedural Statements)

Reading Note of “SystemVerilog for Design” (Chapter 6: SystemVerilog Procedural Blocks, Tasks and Functions)

"always" procedual block Verilog limitation "always" could be combinational or latched or sequential EDA tool must infer design intent from cotent, which might differ from the real intent SystemVerilog improvement New keywords: "always_comb" & "always_latch" & "always_ff" "always_comb" (adv. vs. "always @ *") NO need to specify sensitivity list, auto infer Eliminate the risk of … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 6: SystemVerilog Procedural Blocks, Tasks and Functions)

Reading Note of “SystemVerilog for Design” (Chapter 5: SystemVerilog Arrays, Structures and Unions)

Struct Struct vs. array Array: collection of elements with the same type and size; reference by index Struct: collection of varaibles/constants can be diff types and sizes; reference by name Struct vs. interface Struct usually for variables, can be defined inside of interface Inferface are net type, cannot be defined inside of struct Use "typedef" … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 5: SystemVerilog Arrays, Structures and Unions)

Reading Note of “SystemVerilog for Design” (Chapter 4: SystemVerilog User-Defined and Enumerated Types)

"typedef" keyword Ex. typedef int unsigned uint; Local & shared Local: within a module/interface, scope is limited locally Shared: use package and import; or import to $unit Naming convention End with "_t" as C Enumerated types Verilog vs SystemVerilog Verilog: use constants to represent enumerated types But nothing would limit the value of enum varaibles, … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 4: SystemVerilog User-Defined and Enumerated Types)

Reading Note of “SystemVerilog for Design” (Chapter 3: SystemVerilog Literal Values and Built-in Data Types)

Literal value enhancement Fill vector with all ones Verilog tricks data = ~0; // one's complement data = -1;  // two's complement SystemVerilog: apostrophe(tick) ( ' ) (Note: not back-tick ( ` )) data = '1; // all 1's data = 'z; // all z's DEFINE enhancement String // Verilog  `define print(v) $disp    lay("variable v … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 3: SystemVerilog Literal Values and Built-in Data Types)

Reading Note of “SystemVerilog for Design” (Chapter 2: SystemVerilog Declaration Spaces)

Package Verilog shortage: no global declaration package … endpackage share user-defined type definitions across multiple modules independent of modules parameters cannot be redefined parameter == localparam in package, while in module localparam cannot be directly redefined while instantiation referencing "::" the scope resolution operator package_name::package_member import import package_name::package_member importing an enumerated type definition donot import … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 2: SystemVerilog Declaration Spaces)