Tag: systemverilog

Reading Note of “SystemVerilog for Design” (Chapter 8: Modeling Finite State Machines with SystemVerilog)

This chapter gives some simple example of FSM code featuring SystemVerilog new keywords, such as "enum", "always_comb", "always_ff", "unique case". Modeling FSM with "enum" 3 blocks to model an FSM Incrementing state Determine the next state Set output Using "enum" without explicitly specified value Cause mismatch in value between RTL and gate-level netlist Cause difficulty … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 8: Modeling Finite State Machines with SystemVerilog)

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Reading Note of “SystemVerilog for Design” (Chapter 5: SystemVerilog Arrays, Structures and Unions)

Struct Struct vs. array Array: collection of elements with the same type and size; reference by index Struct: collection of varaibles/constants can be diff types and sizes; reference by name Struct vs. interface Struct usually for variables, can be defined inside of interface Inferface are net type, cannot be defined inside of struct Use "typedef" … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 5: SystemVerilog Arrays, Structures and Unions)

Reading Note of “SystemVerilog for Design” (Chapter 4: SystemVerilog User-Defined and Enumerated Types)

"typedef" keyword Ex. typedef int unsigned uint; Local & shared Local: within a module/interface, scope is limited locally Shared: use package and import; or import to $unit Naming convention End with "_t" as C Enumerated types Verilog vs SystemVerilog Verilog: use constants to represent enumerated types But nothing would limit the value of enum varaibles, … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 4: SystemVerilog User-Defined and Enumerated Types)

Reading Note of “SystemVerilog for Design” (Chapter 3: SystemVerilog Literal Values and Built-in Data Types)

Literal value enhancement Fill vector with all ones Verilog tricks data = ~0; // one's complement data = -1;  // two's complement SystemVerilog: apostrophe(tick) ( ' ) (Note: not back-tick ( ` )) data = '1; // all 1's data = 'z; // all z's DEFINE enhancement String // Verilog  `define print(v) $disp    lay("variable v … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 3: SystemVerilog Literal Values and Built-in Data Types)

Reading Note of “SystemVerilog for Design” (Chapter 2: SystemVerilog Declaration Spaces)

Package Verilog shortage: no global declaration package … endpackage share user-defined type definitions across multiple modules independent of modules parameters cannot be redefined parameter == localparam in package, while in module localparam cannot be directly redefined while instantiation referencing "::" the scope resolution operator package_name::package_member import import package_name::package_member importing an enumerated type definition donot import … Continue reading Reading Note of “SystemVerilog for Design” (Chapter 2: SystemVerilog Declaration Spaces)